1. Field of the Invention
The Present invention relates to an electron beam projection mask, and particularly, to an electron beam projection mask (Electron-Beam exposure mask) for arranging a plurality of batch projection regions on a whole wafer surface.
2. Description of the Related Art
In recent years, in accordance with making high-density integrated circuits, an ultra-microfabrication technology is required for forming a semiconductor element and wiring which form an integrated circuit, and there is a demand for the development of a technique for realizing this circuit.
For example, in order to form a fine pattern having a line width of 0.1 μm or less, when a resist film is exposed, an electron beam is used to form the fine patterning.
Since the electron beam has a very short wavelength as a matter-wave when compared with a wavelength used in other exposure technologies and its diffraction aberration is so small that it can be disregarded, the electron beam exposure essentially has high resolution. However, in the electron beam exposure technique (EB direct drawing), since the pattern is drawn by a rectangular-shaped electron beam with a size of about several μm, the throughput is lowered. This method is called a variable-shaped electron beam exposure method.
In order to improve the throughput, a partial batch electron beam exposure (called a cell projection or block exposure) is used. This partial batch electron beam exposure technology is described, for example, in Publication of Japanese Laid-Open patent. No. 7-161605.
This partial batch electron beam exposure projects a pattern of several μm square area at once which appears repeatedly in a device pattern by using a stencil type electron beam mask (called Si stencil mask, an aperture, a partial batch mask, a cell projection mask, or a block mask) having at least one opening in Si film of about 20 μm of thickness. Accordingly, the number of shots of the electron beam is greatly reduced compared to the conventional EB direct drawing technology, and an improvement of throughput can be attained.
However, even if this partial batch electron beam exposure method is used, for a pattern without the repetition in patterns, the pattern must be directly drawn by the electron beam of the rectangle shape with a size of about several μm square (variable-shaped electron beam exposure method). For this reason, a further improvement in throughput is required for mass-production.
The electron beam exposure method which aims at a high throughput compared to a partial batch electron beam exposure method has been proposed in recent years. In this method, an electron beam reduction projection apparatus using a mask having a circuit pattern for a whole semiconductor chip, irradiates an electron beam at some region of the mask, thus the reduction pattern of the region passes a projection lens and forms an image of the pattern. Generally this technology is called an electron beam projection lithography (abbreviated as EPL). This EPL technology is described in Publication of Japanese Laid-Open patent No. 2000-58446, for example.
Conventionally, the region which can be projected at once by the variable-shaped electron beam exposure method or partial batch exposure method was as small as 5-μm square. However, with the above-mentioned EPL technology, the region which can be projected at once is quite large with 250-micrometer square, and, thereby, the throughput is improved greatly.
However, even if this partial batch electron beam exposure method is used, for a pattern without the repetition in patterns, the pattern must be directly drawn by the electron beam of the rectangle shape with a size of about several μm square (variable-shaped electron beam exposure method). For this reason, a further improvement in a throughput is required in mass-production.
FIGS. 4(a)-(b) are schematic views of a conventional EPL (electron beam projection lithography) mask.
When the size of a batch projection region on a mask is, 1 mm2, a drawing pattern is divided into the size of 1 mm2 as shown in FIG. 4(b).
Finally, when arranging 1 mm2 size batch projection regions on an 8 inch silicon wafer 43, as conventionally shown in FIG. 4(c), they are arranged so that the move distance, i.e., the move time from a certain batch projection region to the next batch projection region to be projected may become short. Therefore, in many cases, each of the batch projection regions is arranged so that the adjacency relations of the original drawing pattern may change as little as possible.
Consequently, the imbalance of the pattern density will arise all over the 8 inch wafer, and according to this imbalance of pattern density, stress occurs at the time of mask manufacturing and electron beam irradiation. Thus curvature and distortion arise on a mask and a wafer. Accordingly, the position accuracy of a pattern worsens.
Since high projection accuracy is one of the important objects of the EPL mask, curvature and distortion of the mask or wafer are problems.
As a technology relevant to this invention, there is a technology described in Publication of Japanese Laid-Open patent No. 7-66098.
However, in the conventional mask manufacturing method, there were problems that the imbalance of pattern density arose all over the wafer, the stress generated at the time of mask manufacturing and electron beam irradiation, the curvature and distortion of a wafer arose, and the position accuracy of a pattern deteriorated.
For example, a manufacturing method of the mask for X-ray steppers is described in Publication of Japanese Laid-Open patent No. 63-110634. In this publication, it is disclosed that since the X-ray stepper uses an X-ray absorbing material having same density for a pattern region and a cover region, shrink and curvature of the X-ray absorbing material by the stress is prevented.
This technology is effective to relieve the stress in a single batch projection region.
However, in this invention, in the case of the mask with which a plurality of batch projection regions are arranged in manner of a matrix, an equalization of the pattern density on the whole wafer surface isn't realized. Rather, there is a possibility of enlarging imbalance of the pattern density on the whole wafer surface, and the stress concentrated on the specific region of the whole wafer surface cannot be prevented.